1. Field of Invention
This invention relates generally to computer system having expansion slots on a mother board (main circuit board) and more specifically, to personal computers including such slots and printed circuit board cards which are adapted to fit in such slots which are connected to a bus, where a portion of the address memory space in the computer is reserved for the slots.
2. Prior Art
Computer systems having expansion slots are well known in the prior art. For example, the Apple IIe is a well known personal computer having expansion slots; memory is reserved for the slots in that computer. However, the memory of a card in that computer is accessed not by first presenting the address but rather by selecting a particular pin in the slot (along with the address) which tells the card in the slot that the address which the microprocessor is calling for is somewhere in that peripheral card's reserved memory. Moreover, the reservation of memory space for cards in these systems is relatively small (e.g. 16-bytes or 256-bytes). That is, the address itself is usually not used alone to indicate when a card's address space is being addressed. Various references are available to one with ordinary skill in the art concerning the general nature of these computer systems. For example: The Apple II Reference Manual, Apple Computer (1981); From Chips to Systems: An Introduction to Microprocessors, Rodnay Zaks, Sybex, Inc., 1981; An Introduction to Microcomputers, by Adam Osborne and Associates, 1975; and The Apple II Circuit Description, Winston Gayler, published by Howard W. Sams & Co., Inc. (1983).
This invention relates more specifically to computer systems using systems buses which follow substantially NUBUS Tm (a trademark of Texas Instruments) bus specifications, which specifications describe the protocols (e.g. logical, electrical and physical standards) and general standards of a sychronous (10 Mhz), multiplexed, multimaster bus which generally provides a fair arbitration mechanism. NUBUS bus originated at the Massachusette Institute of Technology. It has subsequently been revised and exists as published in certain publications of Texas Instruments, Inc. (including Texas Instruments publication number 2242825-0001 and Texas Instrument publication number 2537171-0001). Recently, a committee of the Institute of Electrical and Electronic Engineers (IEEE) has proposed specifications for a system bus, as an IEEE standard, that is substantially a NUBUS bus, although it has been modified from the specifications published by Texas Instruments. The proposed IEEE bus is referred to as the IEEE 1196 Bus. A copy of the proposed specification for the IEEE 1196 Bus (Draft 2.0) is provided with this application for whatever reference may be necessary by one of ordinary skill in the art. The IEEE 1196 Bus is substantially a NUBUS bus as originally specified in Texas Instruments'publications.
In a NUBUS system, there are 4-gigabytes of physical memory address space since there is a 32-bit address bus which may be coupled to a CPU capable of generating 2.sup.32 different addresses. In its simplest form, a computer utilizing the NUBUS bus architecture is essentially a main circuit board having slots into which one place cards (sometimes referred to as modules) having microprocessors, memory and other circuitry generally associated with microcomputers. In effect, each card may itself be a microcomputer which communicates through NUBUS bus to other cards in other slots which are also connected to NUBUS bus. Thus, for example, a NUBUS bus system may include a card having a CPU (central processing unit) microprocessor, a memory management unit, some memory in the form of random access memory (RAM) and read only memory (ROM), and a bus on the card which permits the microprocessor on the card to read the ROM on the card and to read from and write to the RAM on the card. In addition input and output (I/O) circuitry may be included on the card, which circuitry permits the card to communicate through terminals on the card with parts of the rest of the system, including peripheral units such as disk drives, printers, video systems and other peripheral units. The card typically has an edge which includes electrical terminals in the form of pins designed to make electrical connections with cooperating terminals in a slot. Such a card, having a microprocessor, would be capable of mastership of the NUBUS bus by executing certain signals to initiate a NUBUS bus transaction and thereby to transfer and receive information over the NUBUS bus on the main circuit board. Thus, that card could write information to memory located on other cards through NUBUS bus (a transaction) and read that information through NUBUS bus (another transaction).
In the NUBUS bus system, memory is reserved for each of the slots. In the NUBUS bus system, there can be up to 16 slots which are allocated memory space in the upper 1/16 of the entire 4-gigabyte NUBUS bus address space. That upper 16th is 256-megabytes of memory space, and it is divided into 16 regions of 16-megabytes which are mapped to the 16 possible NUBUS bus card slots based on a slot identification number which produces a distinct number at each slot, allowing a card in the slot to "read" the distinct identification number to determine the slot number of the slot into which the card is plugged. See, generally, pages 30-32 of the proposed specification of the IEEE 1196 Bus. Thus, each card gets a "slot space" of 16-megabytes. In the conventional NUBUS bus system, a card's "slot space" is reserved by a device on the card which matches the distinct number (expressed in hexadecimal) of the slot (where the card is) to the second most significant hexadecimal digit (2nd MSHD) of an address appearing on the NUBUS bus, when the address's most significant hexadecimal digit (MSHD) is $F. Thus, the device determines when MSHD equals $F and then determines if the slot number (slot identification number) matches the 2nd MSHD; if there is a match, then the device permits the card to be addressed. Of course, the actual comparison by the card is done in binary, but for purposes of explanation, it is easier to consider the comparison as if it were done in hexadecimal.
This NUBUS bus system provides for considerable flexibility because the vast majority of the memory address space is unreserved. Moreover, the seemingly large (16-megabytes) spaces reserved for the slots (the slot spaces) provide considerable data storage ("data" is used herein to include computer programs). However, too much flexibility fosters incongruities between cards which may be used on the same mother board. That is, this flexibility permits one to design a card which reserves most of the remaining address space in the NUBUS bus system which card would compete with another card developed to use a portion of the same memory space. Of course, switches and jumper cables may be utilized to configure the system to prevent over laps of memory space; however, such solutions are cumbersome in many ways, including their tendancy to frighten novices who would prefer a computer system that permits the user to simply plug the card into a slot and not worry any further.
The present invention solves these problems by allocating automatically 1/16th of the entire memory address space to each slot in the NUBUS bus system. Thus, it is an object of the invention to provide a system which configures itself and which is still flexible but which does not penalize the user because of its flexibility. It is a further object of the invention to provide a main circuit board (mother board) having slots which allow greater automatic computer power due to increased memory space for each card. It is a further object of the invention to provide printed circuit board cards (modules) which automatically configure to their memory space and have increased memory space reserved for each of the cards.
This invention invloves a computer system which has expansion slots coupled to a NUBUS bus, which slots have increased memory space available for and reserved for memory on cards (modules) in the expansion slots and where the reservation of the increased memory occurs by use of distinct identification line means which provides, via a distinct signal, a distinct number identifying the slot number to any card located in the slot. Moreover, the invention provides a card having a decoder means which is coupled to receive the distinct signal provided by the distinct identification line means. A decoder means compares the distinct number provided by the distinct signal to an address appearing on NUBUS bus. The comparison results in 256-megabytes of memory space being reserved for the card in a slot where the memory space ranges from $X000 0000 to $XFFF FFFF, where the slot number is X.
The decoder means compares the distinct number to the most significant hexadecimal digit of the address appearing on the NUBUS bus to determine whether the distinct number, in hexadecimal, is equal to the most significant hexadecimal digit in the address. When the decoder means determines they are equal, it enables any memory on the card to be addressed based on the address appearing on the NUBUS bus. The comparison, of course, is done in binary, but for purposes of explanation, it is easier to consider the comparison process as if it were done in hexadecimal.